A 10b Column-wise Two-step Single-slope ADC for High-speed CMOS Image Sensor

This paper proposes a column-wise two-step SingleSlope (SS) ADC, which improves the sampling rate while maintaining the architecture of the conventional SS-ADC for high-speed CIS. To remove the problem of missing code in multi-stage structures, occurring on every boundary between steps of the coarse ADC, the range of the fine ADC is doubled to cover the boundary. The sampling rate of the ADC is increased by a factor of 2 / (2 + 2) compared to the conventional one. A prototype chip was fabricated in 0.35-μm CMOS process. The proposed ADC has a 10-bit resolution and the sampling rate of 240-kS/s at 25-MHz clock frequency, which has been increased by a factor of 10 compared to the conventional SS-ADC. QVGA imager using the proposed ADC can achieve the theoretical maximum frame rate in excess of 1000-fps with power increase of about 25%.